In the new era of AI infrastructure, CMOS scaling remains the workhorse for heavy computational workloads. But the need for an energy-efficient solution imposes a paradigm shift at the interconnect level, requiring an intimate 3D co-integration of advanced ASICs and optical connectivity.
As the architectural complexity of new products increases, relying on state-of-the-art platforms, with a short path to manufacturing. In this workshop, we will highlight how you can access following technologies for your future products:
- Advanced-node ASIC down to TSMC N2
- Imec’s integrated photonics platforms from 200G up to co-packaged optics
- Imec’s advanced 3D packaging technique from interposer to hybrid bonding
Location: Room 207
Duration: 1 hour
Philippe Soussan
Philippe Soussan is Technology Portfolio Director at imec. For 20 years, he has held different positions in R&D management at imec in the field of sensors, photonics, and 3D packaging. Addressing these technologies from R&D up to manufacturing levels.
His expertise lies in wafer-scale technologies, and he has authored over 100 publications and holds more than 20 patents in these fields.
Since 2024, Philippe has been in charge of strategy definition within the “IC-link by imec” sector. This imec business line provides access to design and manufacturing services in the most advanced ASIC and specialty technologies.
IMEC
Website: https://www.imec-int.com/en
Imec is a world-leading research and innovation center in nanoelectronics and digital technologies. Imec leverages its state-of-the-art R&D infrastructure and team of more than 5,500 employees and top researchers for R&D in advanced semiconductor and system scaling, silicon photonics, artificial intelligence, beyond 5G communications, and sensing technologies.
As imec’s application-specific IC (ASIC) division, imec.IC-link serves start-ups, SMEs, OEMs, and universities by supporting the full ASIC development process from design and IP services to production, packaging, and testing. It realizes over 600 yearly tape-outs in CMOS, Gan-on-SOI, and silicon photonics technologies.
